DVCon is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs) for the design and verification of electronic systems and integrated circuits. The focus of the conference is on specialized languages such as VHDL, PSL, Verilog, SystemVerilog, SystemC, SUPERLOG, e and VERA, as well as general purpose languages such as C and C++. Conference attendees are primarily designers of electronic systems, ASICs and FPGAs, as well as those involved in the research, development and application of Electronic Design Automation (EDA) tools. Presentations are highly technical in nature, and reflect real life experiences in using HDLs and HVLs. We encourage you to contribute your experiences with using hardware design and verification languages and to participate in the valuable exchange of ideas. TOPIC SUGGESTIONS: Any paper, tutorial or panel related to using HDLs, HVLs or other languages you have used for hardware design or verification will be considered. Here are a few topics that conference attendees might find useful: * Experience using ESL and TLM for system-level design and verification * Experiences with System-on-Chip design * Designing verifying complex ASICs and FPGAs * Using multiple HDLs and/or HVLs in a design cycle * Techniques for directed test, random test, or other verification methods * Synthesizing high-level languages such as SystemC, System Verilog or C++ * Experiences with hardware/software co-design * Experiences with mixed-signal simulation * Verification techniques that really work (and what did not work) * Verification methods that have achieved zero functional bugs in first silicon * Assertion-based Verification * Coverage-driven Verification * Design and Verification IP experiences, good and bad * Coverage: code, toggle and functional. Measuring completeness and quality of verification * Experience with formal and Hybrid (dynamic and formal) technologies applied to verification * Any topic involving the use of an HDL or HVL CONFERENCE SCHEDULE: Wednesday, February 22 * Half-day Tutorials am/pm * Exhibits/pm Thursday, February 23 * Opening Keynote Address * Technical sessions * Panel discussions * Exhibits Friday, February 24 * Technical sessions * Panel discussions SUBMITTING A PROPOSAL: Proposals must be submitted on-line at www.dvcon.org. PAPER PROPOSALS: Proposal should be a short abstract of the paper, one to three paragraphs, 300 to 500 words maximum. The abstract must provide enough detail for the program committee to evaluate the technical depth and value of your paper. Be creative with your title! PANEL PROPOSALS: Proposal should be a short abstract of the panel topic, one to three paragraphs, 300 to 500 words maximum. The proposal should include the proposed panel members. Please provide enough detail for the program committee to evaluate the technical depth and value of your panel. SPECIAL SESSION PROPOSALS: Special sessions may consist of embedded tutorials of 1 to 2 hours in length or focused on a specific topic with a list of invited papers/presentations relevant to that topic. Proposals for a special session must contain sufficient information to allow the Technical Program Committee (TPC) to assess the quality and interest of the proposal. Special session proposers will be expected to work closely with the TPC to shape and deliver a high-quality session. SPONSORED TUTORIAL PROPOSALS: A limited number of tutorials that are sponsored will be considered for inclusion in the program. Sponsored tutorials are free to conference registrants and provide an opportunity for an organization to reach an audience that is highly interested in a particular topic. If you are interested in proposing a sponsored tutorial, contact Kathy MacLennan at kathy@mpassociates.com. Sponsored tutorials will be considered on a first-come basis. AUTHOR'S SCHEDULE: * September 13, 2005: Paper, tutorial and panel proposals due * October 28, 2005: Acceptance notification for all types * December 1, 2005: Complete review draft of papers due * January 4, 2006: Final paper due to proceedings printer FINAL PUBLICATION REQUIREMENTS: If your proposed paper is accepted, an author kit with details on paper formatting will be sent to you. Final papers should be between 4 and 8 pages, two-column, single-spaced. Final tutorial materials should include a copy of all presentation slides. SPONSORED BY: The Design and Verification Conference, DVCon, is sponsored by Accellera, www.accellera.org. Accellera is an industry consortium dedicated to the development and standardization of design and verification languages. For more information concerning the conference, please contact the conference management: MP Associates, Inc. 5405 Spine Rd., Ste. 102 Boulder, CO 80301 Telephone: (303) 530-4562 Fax: (303) 530-4334 E-mail: kathy@mpassociates.com ******************************************** Accellera 1370 Trancas Street #163 Napa, CA 94558 Phone (707) 251-9977 Fax (707) 251-9877 www.accellera.org --------------------------------------------------------------------- This list is used to send periodic announcements on upcoming events and other useful information relevant to Accellera's activities and interests. Accellera does not sell or share its list with any other parties. If you would like to unsubscribe from this list please send a message to general_interest-unsubscribe@lists.accellera.org and you will be removed from the Accellera general interest mailing list.